#CANNOT FIND TRI STATE BUFFER IN LOGICWORKS SERIAL#
Port B: 6 bits available, distributed as follows:Ģ bits for controlling the 74HC4094 that controls the upper 8 address bitsġ bit for a reset switch (debounced by the PIC)ġ bit left over (maybe an indicator LED or serial output for a display) Mostly because I'm using a 28-pin DIP for the microcontroller, and once you subtract the 3 I/O lines used for the programming/debug interface, that leaves only 22 I/O lines left. Not sure if this was necessary, but it assured that both changed state at the same time. Instead of toggling bits one at a time, I used a single port, and output the state in one cycle. On thing I did consider when handling both BE and RS, is the IO timing from the microcontroller. Last edited by jmp(FFFA) on Mon 1:51 am, edited 1 time in total. In fact, there is nothing stopping the PIC from programming all 56K (64K-8K) of SRAM either so it could serve not only a role in ROM emulation, but also as a program loader in much the same way flash is used with FPGAs. Eventually I will turn up the clock speed further to see how close to 14 MHz I can get.Ī larger PIC (I don't have anything in DIP form larger than 28-pins at the moment) could control a display, and interface to a FAT filesystem stored on a microSD card. Once the system is up and running correctly, I'll replace the 68B50 with my PIC UART and begin development and testing of that subsystem. Initially, I'll be clocking the 65C02 at 1.8MHz in order to test it with the "real" UARTS I have on hand (68B50s). There's probably other simplifications to be made that I haven't found yet as well. Need to check the gate delays though to make sure it's not worse. I was originally accomplishing this by putting a 74HC245 tri-state buffer on the decoder logic output to the WEn lines on the CY7C199, but it occurs to me that I may be able to slightly simplify the design using another 74HC139 and a leftover gate instead. The only thing special it needs to do is to disallow writes to the last 8K of the SRAM by the 6502, but allow it by the PIC. The address decoding logic is straightforward. The only testing I've done so far is to wire up the data lines to return NOP and then check the address lines for expected operation. When it gets closer to final form, I'll redraw it as several sheets in AD for readability and archival purposes.Ħ502TestBoard.jpg Here are the preliminary schematics for the hardware buffs. Once that's done (hopefully not more than a couple of seconds), the PIC releases the address and data lines it was controlling, enables the 65C02 BE and releases it from reset. Then it loads the contents of the upper 8K of CY7C199 SRAM with a user-specified program. The PIC holds the 65C02 in reset and causes it to release (tri-state) the address and data lines by setting BE low.
It should probably come as no surprise that I'm using another PIC microcontroller to create it. The only potentially interesting thing about this system is the ROM Emulator. Little (preferably no) soldering required.To that end, I've put together a simple design and started building it. As a prelude to testing a PIC-based UART replacement, I find myself in need of a simple 6502-based computer for testing and prototyping purposes.
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